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| mcf5407um/d rev. 0.1, 11/2001 mcf5407 coldfire ? integrated microprocessor user?s manual
?motorola inc., 2001. all rights reserved. coldfire is a registered trademark and digitaldna is a trademark of motorola, inc. i 2 c is a registered trademark of philips semiconductors motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation consequential or incidental damages. ?ypical?parameters which may be provided in motorola data sheets and/or specifications c an and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customer? technical experts. motorola does not convey any license under its pate nt rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applic ation in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purch ase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its offi cers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motor ola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1?03?75?140 or 1?00?41?447 japan: motorola japan ltd.; sps, technical information center, 3?0?, minami?zabu. minato?u, tokyo 106?573 japan. 81??440?569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. 852?6668334 technical information center: 1?00?21?274 home page: http://www.motorola.com/semiconductors document comments : fax (512) 895-2638, attn: tecd applications engineering 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 a part ii part iv part iii 6 glo ind part i overview coldfire core hardware multiply/accumulate (mac) unit local memory debug support sim overview phase-locked loop (pll) i 2 c module interrupt controller chip-select module synchronous/asynchronous dram controller module dma controller module timer module uart modules parallel port (general-purpose i/o) appendix a: migration mechanical data signal descriptions bus operation ieee 1149.1 test access port (jtag) electrical specifications part i: mcf5407 processor core part ii: system integration module ( sim) part iv: hardware interface part iii: peripheral module glossary of terms and abbreviations index appendix b: memory map b 20 b glo ind ind overview coldfire core hardware multiply/accumulate (mac) unit local memory debug support sim overview phase-locked loop (pll) i 2 c module interrupt controller chip-select module synchronous/asynchronous dram controller module dma controller module timer module uart modules parallel port (general-purpose i/o) appendix a: migration mechanical data signal descriptions bus operation ieee 1149.1 test access port (jtag) electrical specifications part i: mcf5407 processor core part ii: system integration module ( sim) part iv: hardware interface part iii: peripheral module glossary of terms and abbreviations index appendix b: memory map 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 a part ii part iv part iii 6 part i 20 b glo ind contents paragraph number title page number contents v chapter 1 overview 1.1 features ............................................................................................................... 1-1 1.2 mcf5407 features.............................................................................................. 1-4 1.2.1 process ............................................................................................................ 1-7 1.3 coldfire module description ............................................................................. 1-7 1.3.1 coldfire core ................................................................................................. 1-7 1.3.1.1 instruction fetch pipeline (ifp).................................................................. 1-7 1.3.1.2 operand execution pipeline (oep) ............................................................ 1-8 1.3.1.3 mac module.............................................................................................. 1-8 1.3.1.4 integer divide module................................................................................ 1-8 1.3.2 harvard architecture ...................................................................................... 1-8 1.3.2.1 16-kbyte instruction cache/8-kbyte data cache ...................................... 1-9 1.3.2.2 internal 2-kbyte srams ............................................................................ 1-9 1.3.3 dram controller ........................................................................................... 1-9 1.3.4 dma controller.............................................................................................. 1-9 1.3.5 uart modules............................................................................................. 1-10 1.3.6 timer module ............................................................................................... 1-11 1.3.7 i 2 c module ................................................................................................... 1-11 1.3.8 system interface ........................................................................................... 1-11 1.3.8.1 external bus interface .............................................................................. 1-11 1.3.8.2 chip selects .............................................................................................. 1-11 1.3.8.3 16-bit parallel port interface .................................................................... 1-12 1.3.8.4 interrupt controller ................................................................................... 1-12 1.3.8.5 jtag......................................................................................................... 1-12 1.3.9 system debug interface................................................................................ 1-12 1.3.10 pll module.................................................................................................. 1-13 1.4 programming model, addressing modes, and instruction set......................... 1-13 1.4.1 programming model ..................................................................................... 1-15 1.4.2 user registers ............................................................................................... 1-15 vi mcf5407 user?s manual contents paragraph number title page number 1.4.3 supervisor registers ..................................................................................... 1-16 1.4.4 instruction set ............................................................................................... 1-16 part i mcf5407 processor core chapter 2 coldfire core 2.1 features and enhancements................................................................................ 2-1 2.1.1 clock-multiplied microprocessor core.......................................................... 2-2 2.1.2 enhanced pipelines ......................................................................................... 2-2 2.1.2.1 instruction fetch pipeline (ifp).................................................................. 2-4 2.1.2.1.1 branch acceleration ............................................................................... 2-4 2.1.2.2 operand execution pipeline (oep) ............................................................ 2-4 2.1.2.2.1 illegal opcode handling......................................................................... 2-5 2.1.2.2.2 hardware multiply/accumulate (mac) unit ........................................ 2-5 2.1.2.2.3 hardware divide unit............................................................................. 2-6 2.1.2.3 harvard memory architecture ................................................................... 2-6 2.1.3 debug module enhancements ........................................................................ 2-6 2.2 programming model ........................................................................................... 2-7 2.2.1 user programming model .............................................................................. 2-8 2.2.1.1 data registers (d0?d7) ............................................................................. 2-8 2.2.1.2 address registers (a0?a6) ........................................................................ 2-9 2.2.1.3 stack pointer (a7, sp) ................................................................................ 2-9 2.2.1.4 program counter (pc) ................................................................................ 2-9 2.2.1.5 condition code register (ccr) ................................................................. 2-9 2.2.1.6 mac programming model....................................................................... 2-10 2.2.2 supervisor programming model................................................................... 2-10 2.2.2.1 status register (sr).................................................................................. 2-11 2.2.2.2 vector base register (vbr) .................................................................... 2-12 2.2.2.3 cache control register (cacr) .............................................................. 2-12 2.2.2.4 access control registers (acr0?acr3)................................................ 2-12 2.2.2.5 ram base address registers (rambar0 and rambar1) ................ 2-12 2.2.2.6 module base address register (mbar) ................................................. 2-12 2.3 integer data formats......................................................................................... 2-13 2.4 organization of data in registers..................................................................... 2-13 2.4.1 organization of integer data formats in registers ...................................... 2-13 2.4.2 organization of integer data formats in memory ....................................... 2-14 2.5 addressing mode summary ............................................................................. 2-15 2.6 instruction set summary................................................................................... 2-15 2.6.1 additions to the instruction set architecture ............................................... 2-18 contents paragraph number title page number contents vii 2.6.2 instruction set summary .............................................................................. 2-19 2.7 execution timings ............................................................................................ 2-23 2.7.1 move instruction execution timing .......................................................... 2-25 2.7.2 execution timings?one-operand instructions .......................................... 2-26 2.7.3 execution timings?two-operand instructions.......................................... 2-27 2.7.4 miscellaneous instruction execution times................................................. 2-29 2.7.5 branch instruction execution times ............................................................ 2-30 2.8 exception processing overview ....................................................................... 2-31 2.8.1 exception stack frame definition................................................................ 2-32 2.8.2 processor exceptions .................................................................................... 2-34 2.9 coldfire instruction set architecture enhancements....................................... 2-36 chapter 3 hardware multiply/accumulate (mac) unit 3.1 overview............................................................................................................. 3-1 3.1.0.1 mac programming model......................................................................... 3-2 3.1.0.2 general operation....................................................................................... 3-3 3.1.0.3 mac instruction set summary .................................................................. 3-4 3.1.0.4 data representation.................................................................................... 3-4 3.2 mac instruction execution timings.................................................................. 3-5 chapter 4 local memory 4.1 interactions between local memory modules ................................................... 4-1 4.2 sram overview ................................................................................................ 4-1 4.3 sram operation ................................................................................................ 4-2 4.4 sram programming model............................................................................... 4-3 4.4.1 sram base address registers (rambar0/rambar1)........................... 4-3 4.5 sram initialization............................................................................................ 4-4 4.5.1 sram initialization code .............................................................................. 4-5 4.6 power management ............................................................................................ 4-6 4.7 cache overview.................................................................................................. 4-6 4.8 cache organization............................................................................................. 4-8 4.8.1 cache line states: invalid, valid-unmodified, and valid-modified............. 4-8 4.8.2 the cache at start-up..................................................................................... 4-9 4.9 cache operation................................................................................................ 4-11 4.9.1 caching modes ............................................................................................. 4-13 4.9.1.1 cacheable accesses .................................................................................. 4-14 4.9.1.2 write-through mode (data cache only)................................................. 4-14 4.9.1.3 copyback mode (data cache only)......................................................... 4-14 viii mcf5407 user?s manual contents paragraph number title page number 4.9.2 cache-inhibited accesses ............................................................................. 4-14 4.9.3 cache protocol.............................................................................................. 4-15 4.9.3.1 read miss ................................................................................................. 4-16 4.9.3.2 write miss (data cache only) ................................................................. 4-16 4.9.3.3 read hit .................................................................................................... 4-16 4.9.3.4 write hit (data cache only) .................................................................... 4-17 4.9.4 cache coherency (data cache only)........................................................... 4-17 4.9.5 memory accesses for cache maintenance................................................... 4-17 4.9.5.1 cache filling............................................................................................. 4-17 4.9.5.2 cache pushes ............................................................................................ 4-18 4.9.5.2.1 push and store buffers ......................................................................... 4-18 4.9.5.2.2 push and store buffer bus operation................................................... 4-18 4.9.6 cache locking .............................................................................................. 4-19 4.10 cache registers................................................................................................. 4-21 4.10.1 cache control register (cacr) .................................................................. 4-21 4.10.2 access control registers (acr0?acr3).................................................... 4-23 4.11 cache management........................................................................................... 4-24 4.12 cache operation summary ............................................................................... 4-27 4.12.1 instruction cache state transitions .............................................................. 4-27 4.12.2 data cache state transitions........................................................................ 4-28 4.13 cache initialization code.................................................................................. 4-32 chapter 5 debug support 5.1 overview............................................................................................................. 5-1 5.2 signal descriptions ............................................................................................. 5-2 5.2.1 processor status/debug data (pstddata[7:0]) ......................................... 5-3 5.3 real-time trace support.................................................................................... 5-4 5.3.1 begin execution of taken branch (pst = 0x5) ............................................. 5-6 5.3.2 processor stopped or breakpoint state change (pst = 0xe) ........................ 5-7 5.3.3 processor halted (pst = 0xf) ........................................................................ 5-7 5.4 programming model ........................................................................................... 5-8 5.4.1 address attribute trigger registers (aatr, aatr1)................................ 5-10 5.4.2 address breakpoint registers (ablr/ablr1, abhr/abhr1) ............. 5-12 5.4.3 bdm address attribute register (baar)................................................... 5-12 5.4.4 configuration/status register (csr)............................................................ 5-13 5.4.5 data breakpoint/mask registers (dbr/dbr1, dbmr/dbmr1) ............ 5-15 5.4.6 program counter breakpoint/mask registers (pbr, pbr1, pbr2, pbr3, pbmr) ........................................................ 5-16 5.4.7 trigger definition register (tdr) ............................................................... 5-18 5.4.8 extended trigger definition register (xtdr) ............................................ 5-19 contents paragraph number title page number contents ix 5.4.9 resulting set of possible trigger combinations.......................................... 5-21 5.5 background debug mode (bdm) .................................................................... 5-22 5.5.1 cpu halt....................................................................................................... 5-22 5.5.2 bdm serial interface.................................................................................... 5-24 5.5.2.1 receive packet format ............................................................................. 5-25 5.5.2.2 transmit packet format............................................................................ 5-26 5.5.3 bdm command set...................................................................................... 5-26 5.5.3.1 coldfire bdm command format............................................................ 5-27 5.5.3.1.1 extension words as required............................................................... 5-28 5.5.3.2 command sequence diagrams................................................................. 5-28 5.5.3.3 command set descriptions ...................................................................... 5-30 5.5.3.3.1 read a/d register ( rareg / rdreg ) ..................................................... 5-30 5.5.3.3.2 write a/d register ( wareg / wdreg )................................................... 5-31 5.5.3.3.3 read memory location ( read )............................................................ 5-32 5.5.3.3.4 write memory location ( write ) ......................................................... 5-33 5.5.3.3.5 dump memory block ( dump ) .............................................................. 5-35 5.5.3.3.6 fill memory block ( fill ) ..................................................................... 5-37 5.5.3.3.7 resume execution ( go )........................................................................ 5-39 5.5.3.3.8 no operation ( nop ) .............................................................................. 5-40 5.5.3.3.9 synchronize pc to the pstddata lines ( sync _ pc ) ........................ 5-41 5.5.3.3.10 read control register ( rcreg ) ............................................................ 5-42 5.5.3.3.11 write control register ( wcreg ) .......................................................... 5-43 5.5.3.3.12 read debug module register ( rdmreg ) ............................................. 5-44 5.5.3.3.13 write debug module register ( wdmreg ) ........................................... 5-45 5.6 real-time debug support ................................................................................ 5-45 5.6.1 theory of operation...................................................................................... 5-46 5.6.1.1 emulator mode ......................................................................................... 5-48 5.6.2 concurrent bdm and processor operation .................................................. 5-48 5.7 motorola-recommended bdm pinout............................................................. 5-49 5.8 debug c definition of pstddata outputs................................................... 5-49 5.8.1 user instruction set ...................................................................................... 5-50 5.8.2 supervisor instruction set............................................................................. 5-53 part ii system integration module (sim) chapter 6 sim overview 6.1 features ............................................................................................................... 6-1 6.2 programming model ........................................................................................... 6-3 6.2.1 sim register memory map............................................................................ 6-3 x mcf5407 user?s manual contents paragraph number title page number 6.2.2 module base address register (mbar) ....................................................... 6-4 6.2.3 reset status register (rsr) ........................................................................... 6-5 6.2.4 software watchdog timer.............................................................................. 6-6 6.2.5 system protection control register (sypcr) ............................................... 6-8 6.2.6 software watchdog interrupt vector register (swivr)............................... 6-9 6.2.7 software watchdog service register (swsr)............................................... 6-9 6.2.8 pll clock control for cpu stop instruction ............................................ 6-10 6.2.9 pin assignment register (par) ................................................................... 6-10 6.2.10 bus arbitration control ................................................................................ 6-11 6.2.10.1 default bus master park register (mpark) .......................................... 6-11 6.2.10.1.1 arbitration for internally generated transfers (mpark[park])...... 6-12 6.2.10.1.2 arbitration between internal and external masters for accessing internal resources ......................................................... 6-14 chapter 7 phase-locked loop (pll) 7.1 overview............................................................................................................. 7-1 7.1.1 pll:pclk ratios........................................................................................... 7-2 7.2 pll operation .................................................................................................... 7-2 7.2.1 reset/initialization .......................................................................................... 7-2 7.2.2 normal mode.................................................................................................. 7-2 7.2.3 reduced-power mode..................................................................................... 7-3 7.2.4 pll control register (pllcr)...................................................................... 7-3 7.3 pll port list....................................................................................................... 7-4 7.4 timing relationships .......................................................................................... 7-4 7.4.1 pclk, pstclk, and bclko ....................................................................... 7-4 7.4.2 rsti timing ................................................................................................... 7-5 7.5 pll power supply filter circuit ........................................................................ 7-6 chapter 8 i 2 c module 8.1 overview............................................................................................................. 8-1 8.2 interface features................................................................................................ 8-1 8.3 i 2 c system configuration................................................................................... 8-3 8.4 i 2 c protocol ........................................................................................................ 8-3 8.4.1 arbitration procedure ..................................................................................... 8-4 8.4.2 clock synchronization.................................................................................... 8-5 8.4.3 handshaking ................................................................................................... 8-5 8.4.4 clock stretching ............................................................................................. 8-5 8.5 programming model ........................................................................................... 8-6 contents paragraph number title page number contents xi 8.5.1 i 2 c address register (iadr) ......................................................................... 8-6 8.5.2 i 2 c frequency divider register (ifdr)......................................................... 8-6 8.5.3 i 2 c control register (i2cr) ........................................................................... 8-7 8.5.4 i 2 c status register (i2sr).............................................................................. 8-8 8.5.5 i 2 c data i/o register (i2dr) ......................................................................... 8-9 8.6 i 2 c programming examples ............................................................................. 8-10 8.6.1 initialization sequence.................................................................................. 8-10 8.6.2 generation of start................................................................................... 8-10 8.6.3 post-transfer software response................................................................. 8-11 8.6.4 generation of stop...................................................................................... 8-12 8.6.5 generation of repeated start................................................................... 8-12 8.6.6 slave mode ................................................................................................... 8-13 8.6.7 arbitration lost............................................................................................. 8-13 chapter 9 interrupt controller 9.1 overview............................................................................................................. 9-1 9.2 interrupt controller registers ............................................................................. 9-2 9.2.1 interrupt control registers (icr0?icr9) ...................................................... 9-3 9.2.2 autovector register (avr) ............................................................................ 9-5 9.2.3 interrupt pending and mask registers (ipr and imr)................................... 9-6 9.2.4 interrupt port assignment register (irqpar) .............................................. 9-7 chapter 10 chip-select module 10.1 overview........................................................................................................... 10-1 10.2 chip-select module signals ............................................................................. 10-1 10.3 chip-select operation....................................................................................... 10-2 10.3.1 general chip-select operation..................................................................... 10-3 10.3.1.1 8-, 16-, and 32-bit port sizing.................................................................. 10-4 10.3.1.2 global chip-select operation................................................................... 10-4 10.4 chip-select registers........................................................................................ 10-5 10.4.1 chip-select module registers ...................................................................... 10-6 10.4.1.1 chip-select address registers (csar0?csar7) ................................... 10-6 10.4.1.2 chip-select mask registers (csmr0?csmr7)...................................... 10-7 10.4.1.3 chip-select control registers (cscr0?cscr7) .................................... 10-8 10.4.1.4 code example........................................................................................... 10-9 chapter 11 synchronous/asynchronous dram controller module xii mcf5407 user?s manual contents paragraph number title page number 11.1 overview........................................................................................................... 11-1 11.1.1 definitions .................................................................................................... 11-2 11.1.2 block diagram and major components ....................................................... 11-2 11.2 dram controller operation ............................................................................ 11-3 11.2.1 dram controller registers ......................................................................... 11-3 11.3 asynchronous operation .................................................................................. 11-4 11.3.1 dram controller signals in asynchronous mode...................................... 11-4 11.3.2 asynchronous register set........................................................................... 11-4 11.3.2.1 dram control register (dcr) in asynchronous mode ........................ 11-4 11.3.2.2 dram address and control registers (dacr0/dacr1) ..................... 11-5 11.3.2.3 dram controller mask registers (dmr0/dmr1) ................................ 11-7 11.3.3 general asynchronous operation guidelines .............................................. 11-8 11.3.3.1 non-page-mode operation..................................................................... 11-11 11.3.3.2 burst page-mode operation ................................................................... 11-12 11.3.3.3 continuous page mode........................................................................... 11-13 11.3.3.4 extended data out (edo) operation..................................................... 11-15 11.3.3.5 refresh operation ................................................................................... 11-16 11.4 synchronous operation................................................................................... 11-16 11.4.1 dram controller signals in synchronous mode...................................... 11-17 11.4.2 using edge select (edgesel) ................................................................. 11-18 11.4.3 synchronous register set ........................................................................... 11-19 11.4.3.1 dram control register (dcr) in synchronous mode......................... 11-19 11.4.3.2 dram address and control registers (dacr0/dacr1) in synchronous mode ......................................................................... 11-20 11.4.3.3 dram controller mask registers (dmr0/dmr1) .............................. 11-22 11.4.4 general synchronous operation guidelines............................................... 11-23 11.4.4.1 address multiplexing ............................................................................. 11-23 11.4.4.2 interfacing example................................................................................ 11-27 11.4.4.3 burst page mode..................................................................................... 11-27 11.4.4.4 continuous page mode........................................................................... 11-29 11.4.4.5 auto-refresh operation.......................................................................... 11-31 11.4.4.6 self-refresh operation ........................................................................... 11-32 11.4.5 initialization sequence................................................................................ 11-32 11.4.5.1 mode register settings........................................................................... 11-33 11.5 sdram example ........................................................................................... 11-34 11.5.1 sdram interface configuration................................................................ 11-34 11.5.2 dcr initialization....................................................................................... 11-35 11.5.3 dacr initialization.................................................................................... 11-35 11.5.4 dmr initialization...................................................................................... 11-37 11.5.5 mode register initialization ....................................................................... 11-38 11.5.6 initialization code....................................................................................... 11-39 contents paragraph number title page number contents xiii part iii peripheral module chapter 12 dma controller module 12.1 overview........................................................................................................... 12-1 12.1.1 dma module features ................................................................................. 12-2 12.2 dma signal description .................................................................................. 12-2 12.3 dma transfer overview.................................................................................. 12-4 12.4 dma controller module programming model................................................ 12-5 12.4.1 source address registers (sar0?sar3) .................................................... 12-7 12.4.2 destination address registers (dar0?dar3) ........................................... 12-7 12.4.3 byte count registers (bcr0?bcr3)........................................................... 12-7 12.4.4 dma control registers (dcr0?dcr3)...................................................... 12-8 12.4.5 dma status registers (dsr0?dsr3) ....................................................... 12-10 12.4.6 dma interrupt vector registers (divr0?divr3) ................................... 12-11 12.5 dma controller module functional description........................................... 12-11 12.5.1 transfer requests (cycle-steal and continuous modes) ........................... 12-12 12.5.2 data transfer modes .................................................................................. 12-12 12.5.2.1 dual-address transfers .......................................................................... 12-12 12.5.2.2 single-address transfers........................................................................ 12-13 12.5.3 channel initialization and startup .............................................................. 12-13 12.5.3.1 channel prioritization ............................................................................. 12-13 12.5.3.2 programming the dma controller module ........................................... 12-13 12.5.4 data transfer .............................................................................................. 12-14 12.5.4.1 external request and acknowledge operation ...................................... 12-14 12.5.4.2 auto-alignment ...................................................................................... 12-17 12.5.4.3 bandwidth control.................................................................................. 12-18 12.5.5 termination................................................................................................. 12-18 chapter 13 timer module 13.1 overview........................................................................................................... 13-1 13.1.1 key features ................................................................................................. 13-2 13.2 general-purpose timer units ........................................................................... 13-2 13.3 general-purpose timer programming model .................................................. 13-2 13.3.1 timer mode registers (tmr0/tmr1) ........................................................ 13-3 13.3.2 timer reference registers (trr0/trr1) ................................................... 13-4 13.3.3 timer capture registers (tcr0/tcr1)....................................................... 13-4 13.3.4 timer counters (tcn0/tcn1) .................................................................... 13-5 xiv mcf5407 user?s manual contents paragraph number title page number 13.3.5 timer event registers (ter0/ter1)........................................................... 13-5 13.4 code example................................................................................................... 13-6 13.5 calculating time-out values ........................................................................... 13-7 chapter 14 uart modules 14.1 overview........................................................................................................... 14-1 14.2 serial module overview ................................................................................... 14-2 14.3 register descriptions ........................................................................................ 14-3 14.3.1 uart mode registers 1 (umr1n).............................................................. 14-5 14.3.2 uart mode register 2 (umr2n) ............................................................... 14-7 14.3.3 rx fifo threshold register (rxlvl)........................................................ 14-8 14.3.4 modem control register (modctl).......................................................... 14-9 14.3.5 tx fifo threshold register (txlvl) ...................................................... 14-10 14.3.6 uart status registers (usrn) ................................................................. 14-10 14.3.7 uart clock-select registers (ucsrn).................................................... 14-12 14.3.8 receive samples available register (rsmp)............................................ 14-12 14.3.9 transmit space available register (tspc) ............................................... 14-13 14.3.10 uart command registers (ucrn) .......................................................... 14-13 14.3.11 uart receiver buffers (urbn) ............................................................... 14-15 14.3.12 uart transmitter buffers (utbn) ........................................................... 14-16 14.3.13 uart input port change registers (uipcrn).......................................... 14-17 14.3.14 uart auxiliary control register (uacrn)............................................. 14-17 14.3.15 uart interrupt status/mask registers (uisrn/uimrn).......................... 14-18 14.3.16 uart divider upper/lower registers (udun/udln) ............................ 14-19 14.3.17 uart interrupt vector register (uivrn)................................................. 14-20 14.3.18 uart input port register (uipn) .............................................................. 14-20 14.3.19 uart output port data registers (uop1n/uop0n)................................. 14-21 14.4 uart module signal definitions .................................................................. 14-21 14.5 operation......................................................................................................... 14-23 14.5.1 transmitter/receiver clock source............................................................ 14-23 14.5.1.1 programmable divider............................................................................ 14-24 14.5.1.2 calculating baud rates........................................................................... 14-24 14.5.1.2.1 clkin baud rates............................................................................. 14-24 14.5.1.2.2 external clock .................................................................................... 14-25 14.5.2 transmitter and receiver operating modes............................................... 14-25 14.5.2.1 transmitting in uart mode ................................................................. 14-26 14.5.2.2 transmitter in modem mode (uart1) ................................................. 14-27 14.5.2.2.1 ac ?97 low-power mode .................................................................. 14-29 14.5.2.3 receiver .................................................................................................. 14-29 14.5.2.4 uart1 in uart mode ......................................................................... 14-31 contents paragraph number title page number contents xv 14.5.2.4.1 receiver in modem mode (uart1).................................................. 14-31 14.5.2.5 fifo stack in uart0............................................................................ 14-32 14.5.2.6 fifos in uart1 .................................................................................... 14-33 14.5.3 looping modes ........................................................................................... 14-34 14.5.3.1 automatic echo mode ............................................................................ 14-34 14.5.3.2 local loop-back mode .......................................................................... 14-34 14.5.3.3 remote loop-back mode....................................................................... 14-35 14.5.4 multidrop mode.......................................................................................... 14-35 14.5.5 bus operation ............................................................................................. 14-37 14.5.5.1 read cycles ............................................................................................ 14-37 14.5.5.2 write cycles ........................................................................................... 14-37 14.5.5.3 interrupt acknowledge cycles ............................................................... 14-37 14.5.6 programming .............................................................................................. 14-37 14.5.6.1 uart module initialization sequence .................................................. 14-38 chapter 15 parallel port (general-purpose i/o) 15.1 parallel port operation...................................................................................... 15-1 15.1.1 pin assignment register (par) ................................................................... 15-1 15.1.2 port a data direction register (paddr).................................................... 15-2 15.1.3 port a data register (padat) .................................................................... 15-2 15.1.4 code example............................................................................................... 15-4 part iv hardware interface chapter 16 mechanical data 16.1 package ............................................................................................................. 16-1 16.2 pinout ................................................................................................................ 16-1 16.3 mechanical diagram......................................................................................... 16-8 16.4 case drawing.................................................................................................... 16-9 chapter 17 signal descriptions 17.1 overview........................................................................................................... 17-1 17.2 mcf5407 bus signals ...................................................................................... 17-7 17.2.1 address bus .................................................................................................. 17-7 xvi mcf5407 user?s manual contents paragraph number title page number 17.2.1.1 address bus (a[23:0]).............................................................................. 17-7 17.2.1.2 address bus (a[31:24]/pp[15:8]) ............................................................ 17-7 17.2.2 data bus (d[31:0]) ....................................................................................... 17-8 17.2.3 read/write (r/w )......................................................................................... 17-8 17.2.4 size (siz[1:0]) .............................................................................................. 17-8 17.2.5 transfer start (ts ) ........................................................................................ 17-9 17.2.6 address strobe (as) ..................................................................................... 17-9 17.2.7 transfer acknowledge (t a ) ......................................................................... 17-9 17.2.8 transfer in progress (tip /pp7)................................................................... 17-10 17.2.9 transfer type (tt[1:0]/pp[1:0]) ................................................................ 17-10 17.2.10 transfer modifier (tm[2:0]/pp[4:2]/dack[1:0])..................................... 17-10 17.3 interrupt control signals................................................................................. 17-12 17.3.1 interrupt request (irq1 /irq2 , irq3 /irq6 , irq5 /irq4 , and irq7 )....... 17-12 17.4 bus arbitration signals................................................................................... 17-12 17.4.1 bus request (br ) ....................................................................................... 17-12 17.4.2 bus grant (bg ).......................................................................................... 17-12 17.4.3 bus driven (bd)......................................................................................... 17-13 17.5 clock and reset signals.................................................................................. 17-13 17.5.1 reset in (rsti )........................................................................................... 17-13 17.5.2 clock input (clkin).................................................................................. 17-13 17.5.3 bus clock output (bclko) ...................................................................... 17-13 17.5.4 reset out (rsto)....................................................................................... 17-13 17.5.5 data/configuration pins (d[7:0]) ............................................................... 17-14 17.5.5.1 d[7:5,3]?boot chip-select (cs0 ) configuration ................................. 17-14 17.5.5.2 d7?auto acknowledge configuration (aa_config) ...................... 17-14 17.5.5.3 d[6:5]?port size configuration (ps_config[1:0]) ........................... 17-14 17.5.5.4 d3?byte-enable configuration (be_config) .................................. 17-15 17.5.6 d4?address configuration (addr_config) ....................................... 17-15 17.5.6.1 d[2:0]?divide control (divide[2:0]) ................................................ 17-15 17.6 chip-select module signals ........................................................................... 17-15 17.6.1 chip-select (cs[7:0]) ................................................................................. 17-15 17.6.2 byte enables/byte write enables (be[3:0]/bwe[3:0]) ............................ 17-16 17.6.3 output enable (oe) .................................................................................... 17-16 17.7 dram controller signals .............................................................................. 17-16 17.7.1 row address strobes (ras[1:0])............................................................... 17-16 17.7.2 column address strobes (cas[3:0]) ......................................................... 17-16 17.7.3 dram write (dramw)........................................................................... 17-16 17.7.4 synchronous dram column address strobe (scas) ............................. 17-17 17.7.5 synchronous dram row address strobe (sras)................................... 17-17 17.7.6 synchronous dram clock enable (scke) .............................................. 17-17 17.7.7 synchronous edge select (edgesel) ...................................................... 17-17 17.8 dma controller module signals.................................................................... 17-17 17.8.1 dma request (dreq[1:0]/pp[6:5]).......................................................... 17-17 contents paragraph number title page number contents xvii 17.8.2 transfer modifier/dma acknowledge (tm[2:0]/dack[1:0]) ................ 17-18 17.9 serial module signals ..................................................................................... 17-18 17.9.1 transmitter serial data output (txd)........................................................ 17-18 17.9.2 receiver serial data input (rxd)............................................................... 17-19 17.9.3 clear to send (cts).................................................................................... 17-19 17.9.4 request to send (rts) ............................................................................... 17-19 17.10 timer module signals..................................................................................... 17-19 17.10.1 timer inputs (tin[1:0]).............................................................................. 17-19 17.10.2 timer outputs (tout1, tout0) .............................................................. 17-19 17.11 parallel i/o port (pp[15:0]) ............................................................................ 17-19 17.12 i 2 c module signals......................................................................................... 17-20 17.12.1 i 2 c serial clock (scl) ............................................................................... 17-20 17.12.2 i 2 c serial data (sda) ................................................................................ 17-20 17.13 debug and test signals .................................................................................. 17-20 17.13.1 test mode (mtmod[3:0]) ........................................................................ 17-20 17.13.2 high impedance (hiz )................................................................................ 17-20 17.13.3 processor clock output (pstclk)............................................................ 17-20 17.13.4 processor status debug data (pstddata[7:0])...................................... 17-21 17.14 debug module/jtag signals......................................................................... 17-21 17.14.1 test reset/development serial clock (trst /dsclk) ............................ 17-21 17.14.2 test mode select/breakpoint (tms/bkpt ) .............................................. 17-21 17.14.3 test data input/development serial input (tdi/dsi) ............................... 17-22 17.14.4 test data output/development serial output (tdo/dso)....................... 17-22 17.14.5 test clock (tck) ....................................................................................... 17-22 chapter 18 bus operation 18.1 features ............................................................................................................. 18-1 18.2 bus and control signals.................................................................................... 18-1 18.3 bus characteristics............................................................................................ 18-2 18.4 data transfer operation ................................................................................... 18-2 18.4.1 bus cycle execution..................................................................................... 18-4 18.4.2 data transfer cycle states ........................................................................... 18-5 18.4.3 read cycle.................................................................................................... 18-7 18.4.4 write cycle ................................................................................................... 18-8 18.4.5 fast-termination cycles............................................................................... 18-9 18.4.6 back-to-back bus cycles ........................................................................... 18-10 18.4.7 burst cycles................................................................................................ 18-11 18.4.7.1 line transfers ......................................................................................... 18-12 18.4.7.2 line read bus cycles............................................................................. 18-12 18.4.7.3 line write bus cycles............................................................................ 18-14 xviii mcf5407 user?s manual contents paragraph number title page number 18.4.7.4 transfers using mixed port sizes .......................................................... 18-15 18.5 misaligned operands ...................................................................................... 18-16 18.6 bus errors ....................................................................................................... 18-17 18.7 interrupt exceptions........................................................................................ 18-17 18.7.1 level 7 interrupts........................................................................................ 18-18 18.7.2 interrupt-acknowledge cycle..................................................................... 18-19 18.8 bus arbitration................................................................................................ 18-20 18.8.1 bus arbitration signals............................................................................... 18-21 18.9 general operation of external master transfers............................................ 18-21 18.9.1 two-device bus arbitration protocol (two-wire mode) ......................... 18-25 18.9.2 multiple external bus device arbitration protocol (three-wire mode)... 18-29 18.10 reset operation............................................................................................... 18-33 18.10.1 master reset ............................................................................................... 18-34 18.10.2 software watchdog reset........................................................................... 18-35 chapter 19 ieee 1149.1 test access port (jtag) 19.1 overview........................................................................................................... 19-1 19.2 jtag signal descriptions ............................................................................... 19-2 19.3 tap controller.................................................................................................. 19-3 19.4 jtag register descriptions ............................................................................. 19-4 19.4.1 jtag instruction shift register .................................................................. 19-5 19.4.2 idcode register ......................................................................................... 19-6 19.4.3 jtag boundary-scan register .................................................................... 19-7 19.4.4 jtag bypass register................................................................................ 19-10 19.5 restrictions ..................................................................................................... 19-10 19.6 disabling ieee standard 1149.1 operation ................................................... 19-10 19.7 obtaining the ieee standard 1149.1.............................................................. 19-11 chapter 20 electrical specifications 20.1 general parameters ........................................................................................... 20-1 20.1.1 supply voltage sequencing and separation cautions.................................. 20-3 20.2 clock timing specifications............................................................................. 20-4 20.3 input/output ac timing specifications........................................................... 20-6 20.4 reset timing specifications ........................................................................... 20-15 20.5 debug ac timing specifications................................................................... 20-16 20.6 timer module ac timing specifications ...................................................... 20-17 20.7 i 2 c input/output timing specifications......................................................... 20-18 20.8 uart module ac timing specifications ..................................................... 20-19 contents paragraph number title page number contents xix 20.9 parallel port (general-purpose i/o) timing specifications ........................... 20-22 20.10 dma timing specifications........................................................................... 20-23 20.11 ieee 1149.1 (jtag) ac timing specifications ........................................... 20-24 appendix a migrating from the coldfire mcf5307 to the mcf5407 a.1 overview............................................................................................................ a-1 a.2 instruction set additions ................................................................................... a-2 a.3 enhanced memories........................................................................................... a-3 a.4 on-chip dma modifications............................................................................ a-4 a.5 uart enhancements ........................................................................................ a-5 a.6 timing differences ............................................................................................ a-6 a.6.1 phase-locked loop (pll)............................................................................. a-6 a.6.2 timing relationships..................................................................................... a-7 a.7 reset initialization modifications...................................................................... a-8 a.8 revision c debug ............................................................................................ a-10 a.8.1 debug interrupts and interrupt requests in emulator mode .................................................................................... a-10 a.8.2 on-chip breakpoint registers..................................................................... a-12 a.8.2.1 write debug module register (wdmreg) ................................................ a-12 a.8.3 debug programming model ........................................................................ a-14 a.8.3.1 address breakpoint 1 registers (ablr1, abhr1) ............................... a-14 a.8.3.2 address attribute breakpoint register 1 (aatr1) ................................ a-14 a.8.3.3 program counter breakpoint registers 1?3 (pbr1?pbr3) ................... a-14 a.8.3.4 data breakpoint register 1 (dbr1, dbmr1) ........................................ a-15 a.8.3.5 extended trigger definition register (xtdr) ....................................... a-15 a.8.4 debug interrupt exception vectors ............................................................. a-15 a.8.5 processor status and debug data output signals ....................................... a-16 a.8.6 debug c summary....................................................................................... a-17 a.9 voltage input changes..................................................................................... a-17 a.10 pll power supply filter circuit ..................................................................... a-18 a.11 pin-assignment compatibility......................................................................... a-18 appendix b list of memory maps xx mcf5407 user?s manual contents paragraph number title page number illustrations figure number title page number illustrations xxi 1-1 mcf5407 block diagram............................................................................................. 1-2 1-2 uart module block diagram................................................................................... 1-10 1-3 pll module ................................................................................................................ 1- 13 1-4 coldfire mcf5407 programming model .................................................................. 1-15 2-1 coldfire enhanced pipeline ......................................................................................... 2-3 2-2 coldfire multiply-accumulate functionality diagram ............................................... 2-5 2-3 coldfire programming model...................................................................................... 2-8 2-4 condition code register (ccr) ................................................................................... 2-9 2-5 status register (sr).................................................................................................... 2-11 2-6 vector base register (vbr)....................................................................................... 2-12 2-7 organization of integer data formats in data registers............................................ 2-13 2-8 organization of integer data formats in address registers ...................................... 2-14 2-9 memory operand addressing..................................................................................... 2-14 2-1 exception stack frame form...................................................................................... 2-33 3-1 coldfire mac multiplication and accumulation........................................................ 3-2 3-2 mac programming model ........................................................................................... 3-2 4-1 sram base address registers (rambarn) ............................................................. 4-3 4-2 data cache organization .............................................................................................. 4-7 4-3 data cache organization and line format .................................................................. 4-8 4-4 data cache?a: at reset, b: after invalidation, c and d: loading pattern............... 4-10 4-5 data caching operation.............................................................................................. 4-11 4-6 write-miss in copyback mode................................................................................... 4-16 4-7 data cache locking.................................................................................................... 4-20 4-8 cache control register (cacr) ................................................................................ 4-21 4-9 access control register format (acrn) ................................................................... 4-24 4-10 an format (data cache)............................................................................................. 4-25 4-11 an format (instruction cache) ................................................................................... 4-25 4-12 instruction cache line state diagram........................................................................ 4-27 4-13 data cache line state diagram?copyback mode ................................................... 4-28 4-14 data cache line state diagram?write-through mode ........................................... 4-29 5-1 processor/debug module interface............................................................................... 5-1 5-2 pstclk timing........................................................................................................... 5-3 5-3 pstddata: single-cycle instruction timing............................................................ 5-3 5-4 example jmp instruction output on pstddata....................................................... 5-6 5-5 debug programming model ......................................................................................... 5-9 5-6 address attribute trigger registers (aatr, aatr1).............................................. 5-11 illustrations figure number title page number xxii mcf5407 user?s manual 5-7 address breakpoint registers (ablr, abhr, ablr1, abhr1)............................ 5-12 5-8 bdm address attribute register (baar)................................................................. 5-13 5-9 configuration/status register (csr).......................................................................... 5-13 5-10 data breakpoint/mask registers (dbr/dbr1 and dbmr/dbmr1)....................... 5-16 5-11 program counter breakpoint registers (pbr, pbr1, pbr2, pbr3) ........................ 5-17 5-12 program counter breakpoint mask register (pbmr) ............................................... 5-17 5-13 trigger definition register (tdr) ............................................................................. 5-18 5-14 extended trigger definition register (xtdr) .......................................................... 5-20 5-15 bdm serial interface timing ..................................................................................... 5-24 5-16 receive bdm packet.................................................................................................. 5-25 5-17 transmit bdm packet ................................................................................................ 5-26 5-18 bdm command format ............................................................................................. 5-27 5-19 command sequence diagram..................................................................................... 5-29 5-21 rareg / rdreg command sequence............................................................................ 5-30 5-20 rareg / rdreg command format ............................................................................... 5-30 5-23 wareg / wdreg command sequence .......................................................................... 5-31 5-22 wareg / wdreg command format.............................................................................. 5-31 5-25 read command sequence.......................................................................................... 5-32 5-24 read command/result formats................................................................................... 5-32 5-26 write command format ............................................................................................ 5-33 5-27 write command sequence ........................................................................................ 5-34 5-28 dump command/result formats ................................................................................ 5-35 5-29 dump command sequence ......................................................................................... 5-36 5-30 fill command format................................................................................................ 5-37 5-31 fill command sequence............................................................................................ 5-38 5-33 go command sequence.............................................................................................. 5-39 5-32 go command format.................................................................................................. 5-39 5-35 nop command sequence ............................................................................................ 5-40 5-34 nop command format................................................................................................ 5-40 5-37 sync _ pc command sequence .................................................................................... 5-41 5-36 sync _ pc command format........................................................................................ 5-41 5-39 rcreg command sequence........................................................................................ 5-42 5-38 rcreg command/result formats............................................................................... 5-42 5-41 wcreg command sequence ....................................................................................... 5-43 5-40 wcreg command/result formats.............................................................................. 5-43 5-43 rdmreg command sequence..................................................................................... 5-44 5-42 rdmreg bdm command/result formats.................................................................... 5-44 5-45 wdmreg command sequence .................................................................................... 5-45 5-44 wdmreg bdm command format.............................................................................. 5-45 5-46 recommended bdm connector................................................................................. 5-49 6-1 sim block diagram...................................................................................................... 6-1 6-2 module base address register (mbar) ..................................................................... 6-4 6-3 reset status register (rsr) ......................................................................................... 6-5 illustrations figure number title page number illustrations xxiii 6-4 mcf5407 embedded system recovery from unterminated access........................... 6-7 6-5 system protection control register (sypcr) ............................................................ 6-8 6-6 software watchdog interrupt vector register (swivr)............................................ 6-9 6-7 software watchdog service register (swsr)............................................................ 6-9 6-8 pin assignment register (par) ................................................................................. 6-10 6-9 default bus master register (mpark) ..................................................................... 6-11 6-10 round robin arbitration (park = 00)...................................................................... 6-12 6-11 park on master core priority (park = 01) ............................................................... 6-13 6-12 park on dma module priority (park = 10)............................................................. 6-13 6-13 park on current master priority (park = 01) ........................................................... 6-14 7-1 pll module block diagram ........................................................................................ 7-1 7-2 pll control register (pllcr).................................................................................... 7-3 7-3 clkin, pclk, pstclk, and bclko timing .......................................................... 7-5 7-4 reset and initialization timing..................................................................................... 7-6 7-5 pll power supply filter circuit ................................................................................. 7-6 8-1 i 2 c module block diagram .......................................................................................... 8-2 8-2 i 2 c standard communication protocol ........................................................................ 8-3 8-3 repeated start .......................................................................................................... 8-4 8-4 synchronized clock scl.............................................................................................. 8-5 8-5 i 2 c address register (iadr) ....................................................................................... 8-6 8-6 i 2 c frequency divider register (ifdr)....................................................................... 8-7 8-7 i 2 c control register (i2cr) ......................................................................................... 8-8 8-8 i 2 cr status register (i2sr) ......................................................................................... 8-9 8-9 i 2 c data i/o register (i2dr) ..................................................................................... 8-10 8-10 flow-chart of typical i2c interrupt routine............................................................. 8-14 9-1 interrupt controller block diagram.............................................................................. 9-1 9-2 interrupt control registers (icr0?icr9) .................................................................... 9-3 9-3 autovector register (avr) .......................................................................................... 9-5 9-4 interrupt pending register (ipr) and interrupt mask register (imr) ......................... 9-7 9-5 interrupt port assignment register (irqpar) ............................................................ 9-7 10-1 connections for external memory port sizes ............................................................ 10-4 10-2 chip select address registers (csar0?csar7) ..................................................... 10-6 10-3 chip select mask registers (csmrn) ....................................................................... 10-7 10-4 chip-select control registers (cscr0?cscr7) ...................................................... 10-8 11-1 asynchronous/synchronous dram controller block diagram ............................... 11-2 11-2 dram control register (dcr) (asynchronous mode) ............................................ 11-5 11-3 dram address and control registers (dacr0/dacr1)........................................ 11-6 11-4 dram controller mask registers (dmr0 and dmr1)............................................ 11-7 11-5 basic non-page-mode operation rcd = 0, rncn = 1 (4-4-4-4) .......................... 11-11 11-6 basic non-page-mode operation rcd = 1, rncn = 0 (5-5-5-5) .......................... 11-12 11-7 burst page-mode read operation (4-3-3-3)............................................................. 11-13 11-8 burst page-mode write operation (4-3-3-3)............................................................ 11-13 11-9 continuous page-mode operation............................................................................ 11-14 illustrations figure number title page number xxiv mcf5407 user?s manual 11-10 write hit in continuous page mode......................................................................... 11-15 11-11 edo read operation (3-2-2-2) ................................................................................ 11-15 11-12 dram access delayed by refresh ......................................................................... 11-16 11-13 mcf5407 sdram interface.................................................................................... 11-18 11-14 using edgesel to change signal timing............................................................. 11-19 11-15 dram control register (dcr) (synchronous mode) ............................................ 11-19 11-16 dacr0 and dacr1 registers (synchronous mode).............................................. 11-20 11-17 dram controller mask registers (dmr0 and dmr1).......................................... 11-22 11-18 burst read sdram access ..................................................................................... 11-28 11-19 burst write sdram access .................................................................................... 11-29 11-20 synchronous, continuous page-mode access?consecutive reads....................... 11-30 11-21 synchronous, continuous page-mode access?read after write........................... 11-31 11-22 auto-refresh operation............................................................................................ 11-32 11-23 self-refresh operation ............................................................................................. 11-32 11-24 mode register set (mrs) command ......................................................................... 11-34 11-25 initialization values for dcr ................................................................................... 11-35 11-26 sdram configuration............................................................................................. 11-36 11-27 dacr register configuration.................................................................................. 11-36 11-28 dmr0 register ......................................................................................................... 11-3 7 11-29 mode register mapping to mcf5407 a[31:0] ........................................................ 11-38 12-1 dma signal diagram ................................................................................................. 12-1 12-2 mcf5307/mcf5407 tm[2:0] pin remapping .......................................................... 12-4 12-3 dual-address transfer................................................................................................ 12-4 12-4 single-address transfers............................................................................................ 12-5 12-6 destination address registers (darn) ...................................................................... 12-7 12-5 source address registers (sarn) .............................................................................. 12-7 12-7 byte count registers (bcrn)..................................................................................... 12-8 12-8 dma control registers (dcrn) ............................................................................... 12-8 12-9 dma status registers (dsrn) ................................................................................ 12-10 12-10 dma interrupt vector registers (divrn) ............................................................... 12-11 12-11 dreq timing constraints, dual-address dma transfer....................................... 12-15 12-12 dual-address, peripheral-to-sdram, lower-priority dma transfer ................... 12-16 12-13 single-address dma transfer ................................................................................. 12-17 13-1 timer block diagram ................................................................................................. 13-1 13-2 timer mode registers (tmr0/tmr1) ...................................................................... 13-3 13-3 timer reference registers (trr0/trr1) ................................................................. 13-4 13-4 timer capture register (tcr0/tcr1) ...................................................................... 13-5 13-5 timer counters (tcn0/tcn1)................................................................................... 13-5 13-6 timer event registers (ter0/ter1)......................................................................... 13-5 14-1 simplified block diagram .......................................................................................... 14-1 14-2 uart mode registers 1 (umr1n)............................................................................ 14-6 14-3 uart mode register 2 (umr2n) ............................................................................. 14-7 14-4 rx fifo threshold register (rxlvl)...................................................................... 14-8 illustrations figure number title page number illustrations xxv 14-5 modem control register (modctl) ........................................................................ 14-9 14-6 tx fifo threshold register (txlvl) .................................................................... 14-10 14-7 uart status register (usrn) ................................................................................. 14-10 14-8 uart clock-select register (ucsrn).................................................................... 14-12 14-9 receive samples available register (rsmp).......................................................... 14-13 14-10 tx space available register (tspc) ....................................................................... 14-13 14-11 uart command register (ucrn).......................................................................... 14-14 14-12 uart receiver buffer for uart0 (urb0)............................................................ 14-16 14-13 uart receiver buffer for uart1 (urb1)............................................................ 14-16 14-14 uart transmitter buffer for uart0 (utb0) ....................................................... 14-16 14-15 uart transmitter buffer for uart1 (utb1) ....................................................... 14-17 14-16 uart input port change register (uipcrn).......................................................... 14-17 14-17 uart auxiliary control register (uacrn) ........................................................... 14-18 14-18 uart interrupt status/mask registers (uisrn/uimrn)........................................ 14-18 14-19 uart divider upper register (udun)................................................................... 14-19 14-20 uart divider lower register (udln)................................................................... 14-19 14-21 uart interrupt vector register (uivrn) ............................................................... 14-20 14-22 uart input port register (uipn) ............................................................................ 14-20 14-24 uart block diagram showing external and internal interface signals ................ 14-21 14-23 uart output port data 1 register (uop1/uop0) ................................................. 14-21 14-25 uart/rs-232 interface ........................................................................................... 14-23 14-26 uart1/codec interface........................................................................................ 14-23 14-27 uart1/ac ?97 interface ......................................................................................... 14-23 14-28 clocking source diagram......................................................................................... 14-24 14-29 transmitter and receiver functional diagram......................................................... 14-25 14-30 transmitter timing diagram .................................................................................... 14-27 14-31 16-bit codec interface timing (lsb first) ............................................................. 14-27 14-32 8-bit codec interface timing (msb first) ............................................................. 14-28 14-33 ac ?97 interface timing........................................................................................... 14-28 14-34 receiver timing........................................................................................................ 14- 30 14-35 automatic echo ........................................................................................................ 14-3 4 14-36 local loop-back ...................................................................................................... 14-34 14-37 remote loop-back ................................................................................................... 14-35 14-38 multidrop mode timing diagram ............................................................................ 14-36 14-39 uart mode programming flowchart ..................................................................... 14-39 15-1 parallel port pin assignment register (par) ............................................................ 15-1 15-2 port a data direction register (paddr).................................................................. 15-2 15-3 port a data register (padat) .................................................................................. 15-3 16-1 mechanical diagram................................................................................................... 16-9 16-2 mcf5407 case drawing (general view) ................................................................ 16-10 16-3 case drawing (details)............................................................................................. 16-11 17-1 mcf5407 block diagram with signal interfaces ...................................................... 17-2 17-2 mcf5307 to mcf5407 tm[2:0] pin remapping .................................................... 17-18 illustrations figure number title page number xxvi mcf5407 user?s manual 18-1 signal relationship to clkin for non-dram access............................................. 18-2 18-2 connections for external memory port sizes ............................................................ 18-4 18-3 chip-select module output timing diagram ............................................................ 18-4 18-4 data transfer state transition diagram ..................................................................... 18-6 18-5 read cycle flowchart................................................................................................. 18-7 18-6 basic read bus cycle................................................................................................. 18-8 18-7 write cycle flowchart................................................................................................ 18-9 18-8 basic write bus cycle ................................................................................................ 18-9 18-9 read cycle with fast termination ........................................................................... 18-10 18-10 write cycle with fast termination........................................................................... 18-10 18-11 back-to-back bus cycles ......................................................................................... 18-11 18-12 line read burst (2-1-1-1), external termination .................................................... 18-12 18-13 line read burst (2-1-1-1), internal termination ..................................................... 18-13 18-14 line read burst (3-2-2-2), external termination .................................................... 18-13 18-15 line read burst-inhibited, fast, external termination............................................ 18-14 18-16 line write burst (2-1-1-1), internal/external termination...................................... 18-14 18-17 line write burst (3-2-2-2) with one wait state, internal termination ................... 18-15 18-18 line write burst-inhibited, internal termination .................................................... 18-15 18-19 longword read from an 8-bit port, external termination...................................... 18-16 18-20 longword read from an 8-bit port, internal termination ....................................... 18-16 18-21 example of a misaligned longword transfer (32-bit port) .................................... 18-17 18-22 example of a misaligned word transfer (32-bit port) ............................................ 18-17 18-23 interrupt-acknowledge cycle flowchart ................................................................. 18-20 18-24 basic no-wait-state external master access .......................................................... 18-22 18-25 external master burst line access to 32-bit port.................................................... 18-24 18-26 mcf5407 two-wire mode bus arbitration interface............................................. 18-25 18-27 two-wire bus arbitration with bus request asserted............................................ 18-26 18-28 two-wire implicit and explicit bus mastership...................................................... 18-27 18-29 mcf5407 two-wire bus arbitration protocol state diagram................................ 18-28 18-30 three-wire implicit and explicit bus mastership.................................................... 18-30 18-31 three-wire bus arbitration...................................................................................... 18-31 18-32 three-wire bus arbitration protocol state diagram ............................................... 18-32 18-33 master reset timing................................................................................................. 18-34 18-34 software watchdog reset timing ............................................................................ 18-35 19-1 jtag test logic block diagram ............................................................................... 19-2 19-2 jtag tap controller state machine......................................................................... 19-4 19-3 idcode register ....................................................................................................... 19-6 19-4 disabling jtag in jtag mode ............................................................................... 19-11 19-5 disabling jtag in debug mode .............................................................................. 19-11 20-1 supply voltage sequencing and separation cautions................................................ 20-3 20-2 example circuit to control supply sequencing......................................................... 20-4 20-3 clkin-to-core clock frequency ranges.................................................................. 20-4 20-4 clock timing .............................................................................................................. 2 0-5 illustrations figure number title page number illustrations xxvii 20-5 pstclk timing......................................................................................................... 20-6 20-6 ac timings?normal read and write bus cycles ................................................... 20-8 20-7 sdram read cycle with edgesel tied to buffered clkin ............................... 20-9 20-8 sdram write cycle with edgesel tied to buffered clkin ............................ 20-10 20-9 sdram read cycle with edgesel tied high..................................................... 20-11 20-10 sdram write cycle with edgesel tied high.................................................... 20-12 20-11 sdram read cycle with edgesel tied low ..................................................... 20-13 20-12 sdram write cycle with edgesel tied low .................................................... 20-14 20-13 ac output timing?high impedance...................................................................... 20-14 20-14 reset timing............................................................................................................. 2 0-15 20-15 real-time trace ac timing .................................................................................... 20-16 20-16 bdm serial port ac timing .................................................................................... 20-16 20-17 timer module ac timing ........................................................................................ 20-17 20-18 i 2 c input/output timings ......................................................................................... 20-19 20-19 uart0 and uart1 module ac timing?uart mode ....................................... 20-20 20-20 uart1 in 8- and 16-bit codec mode ................................................................... 20-21 20-21 uart1 in ac ?97 mode .......................................................................................... 20-21 20-22 general-purpose i/o timing..................................................................................... 20-22 20-23 dma timing ............................................................................................................ 20-2 3 20-24 ieee 1149.1 (jtag) ac timing ............................................................................. 20-25 a-1 mcf5307 to mcf5407 tm[2:0] pin remapping ....................................................... a-5 a-2 simplified block diagram ........................................................................................... a-6 a-3 pll module................................................................................................................. a -7 a-4 exception stack frame form .................................................................................... a-11 a-5 write debug module register command ( wdmreg )............................................... a-12 a-6 wdmreg command sequence................................................................................... a-13 a-7 pll power supply filter circuit............................................................................... a-18 illustrations figure number title page number xxviii mcf5407 user?s manual tables xxix tables table number title page number 9/1/00 1-1 user-level registers................................................................................................... 1-15 1-2 supervisor-level registers......................................................................................... 1-16 2-1 ccr field descriptions ............................................................................................. 2-10 2-2 movec register map ............................................................................................... 2-11 2-3 status field descriptions ............................................................................................ 2-11 2-4 integer data formats................................................................................................... 2-13 2-5 coldfire effective addressing modes........................................................................ 2-15 2-6 notational conventions .............................................................................................. 2-16 2-7 coldfire isa_b extension summary......................................................................... 2-19 2-8 user-level instruction set summary.......................................................................... 2-19 2-9 supervisor-level instruction set summary................................................................ 2-23 2-10 misaligned operand references ................................................................................. 2-24 2-11 move byte and word execution times...................................................................... 2-25 2-12 move long execution times...................................................................................... 2-25 2-13 miscellaneous move execution times....................................................................... 2-26 2-14 one-operand instruction execution times ................................................................ 2-27 2-15 two-operand instruction execution times................................................................ 2-27 2-16 miscellaneous instruction execution times............................................................... 2-29 2-17 branch instruction execution times .......................................................................... 2-30 2-18 bcc instruction execution times................................................................................ 2-30 2-19 exception vector assignments................................................................................... 2-32 2-20 format field encoding ............................................................................................... 2-33 2-21 fault status encodings................................................................................................ 2-33 2-22 mcf5407 exceptions ................................................................................................. 2-34 3-1 mac instruction summary........................................................................................... 3-4 3-2 two-operand mac instruction execution times ....................................................... 3-5 3-3 mac move instruction execution times..................................................................... 3-6 4-1 rambarn field description ...................................................................................... 4-3 4-2 examples of typical rambar settings ..................................................................... 4-6 4-3 valid and modified bit settings ................................................................................... 4-8 4-4 cacr field descriptions ........................................................................................... 4-21 4-5 acrn field descriptions............................................................................................ 4-24 4-6 instruction cache line state transitions.................................................................... 4-27 4-7 data cache line state transitions.............................................................................. 4-29 4-8 data cache line state transitions (current state invalid) ........................................ 4-30 4-9 data cache line state transitions (current state valid)........................................... 4-31 xxx mcf5407 user?s manual tables table number title page number 4-10 data cache line state transitions (current state modified)..................................... 4-31 5-1 debug module signals.................................................................................................. 5-2 5-2 pstddata: sequential execution of single-cycle instructions .............................. 5-3 5-3 pstddata: data operand captured.......................................................................... 5-4 5-4 processor status encoding............................................................................................ 5-5 5-5 0xe status posting ........................................................................................................ 5- 7 5-6 bdm/breakpoint registers........................................................................................... 5-9 5-7 aatr and aatr1 field descriptions....................................................................... 5-11 5-8 ablr and ablr1 field description......................................................................... 5-12 5-9 abhr and abhr1 field description........................................................................ 5-12 5-10 baar field descriptions ........................................................................................... 5-13 5-11 csr field descriptions............................................................................................... 5-14 5-12 dbrn field descriptions............................................................................................ 5-16 5-13 dbmrn field descriptions ........................................................................................ 5-16 5-14 access size and operand data location .................................................................... 5-16 5-15 pbr, pbr1, pbr2, pbr3 field descriptions............................................................ 5-17 5-16 pbmr field descriptions ........................................................................................... 5-17 5-17 tdr field descriptions .............................................................................................. 5-19 5-18 xtdr field descriptions ........................................................................................... 5-20 5-19 receive bdm packet field description ..................................................................... 5-25 5-20 transmit bdm packet field description ................................................................... 5-26 5-21 bdm command summary ......................................................................................... 5-26 5-22 bdm field descriptions ............................................................................................. 5-27 5-23 control register map.................................................................................................. 5-42 5-24 definition of drc encoding?read........................................................................... 5-44 5-25 pstddata nibble/csr[bstat] breakpoint response......................................... 5-46 5-26 exception vector assignments................................................................................... 5-47 5-27 pstddata specification for user-mode instructions............................................. 5-50 5-28 pstddata specification for supervisor-mode instructions ................................... 5-54 6-1 sim registers ............................................................................................................. . 6-3 6-2 mbar field descriptions ............................................................................................ 6-5 6-3 rsr field descriptions................................................................................................. 6-6 6-4 sypcr field descriptions ........................................................................................... 6-8 6-5 pllipl settings.......................................................................................................... 6-1 0 6-6 mpark field descriptions........................................................................................ 6-11 7-1 divide ratio encodings ............................................................................................... 7-2 7-2 pllcr field descriptions............................................................................................ 7-3 7-3 pll module input signals............................................................................................ 7-4 7-4 pll module output signals ......................................................................................... 7-4 8-1 i 2 c interface memory map........................................................................................... 8-6 8-2 i 2 c address register field descriptions ...................................................................... 8-6 8-3 ifdr field descriptions ............................................................................................... 8-7 8-4 i 2 cr field descriptions................................................................................................ 8-8 tables xxxi tables table number title page number 8-5 i2sr field descriptions................................................................................................ 8-9 9-1 interrupt controller registers ....................................................................................... 9-2 9-2 interrupt control registers ........................................................................................... 9-2 9-3 icrn field descriptions ............................................................................................... 9-3 9-4 interrupt priority scheme.............................................................................................. 9-4 9-5 avr field descriptions................................................................................................ 9-6 9-6 autovector register bit assignments........................................................................... 9-6 9-7 ipr and imr field descriptions................................................................................... 9-7 9-8 irqpar field descriptions ......................................................................................... 9-8 10-1 chip-select module signals ....................................................................................... 10-1 10-2 byte enables/byte write enable signal settings ....................................................... 10-2 10-3 accesses by matches in cscrs and dacrs ............................................................. 10-3 10-4 d7/aa, automatic acknowledge of boot cs0.......................................................... 10-4 10-5 d[6:5]/ps[1:0], port size of boot cs0 ....................................................................... 10-5 10-6 d3/be_config0, be [3:0] boot configuration ....................................................... 10-5 10-7 chip-select registers.................................................................................................. 10-5 10-8 csarn field description ........................................................................................... 10-7 10-9 csmrn field descriptions ......................................................................................... 10-7 10-10 cscrn field descriptions.......................................................................................... 10-8 11-1 dram controller registers ....................................................................................... 11-3 11-2 sdram signal summary .......................................................................................... 11-4 11-3 dcr field descriptions (asynchronous mode)......................................................... 11-5 11-4 dacr0/dacr1 field description ............................................................................ 11-6 11-5 dmr0/dmr1 field descriptions............................................................................... 11-7 11-6 generic address multiplexing scheme ...................................................................... 11-8 11-7 dram addressing for byte-wide memories.......................................................... 11-10 11-8 dram addressing for 16-bit wide memories........................................................ 11-10 11-9 dram addressing for 32-bit wide memories........................................................ 11-11 11-10 sdram commands ................................................................................................. 11-17 11-11 synchronous dram signal connections ................................................................ 11-17 11-12 dcr field descriptions (synchronous mode) ......................................................... 11-19 11-13 dacr0/dacr1 field descriptions (synchronous mode)...................................... 11-21 11-14 dmr0/dmr1 field descriptions............................................................................. 11-23 11-15 mcf5407 to sdram interface (8-bit port, 9-column address lines).................. 11-24 11-16 mcf5407 to sdram interface (8-bit port,10-column address lines)................. 11-24 11-17 mcf5407 to sdram interface (8-bit port,11-column address lines)................. 11-24 11-18 mcf5407 to sdram interface (8-bit port,12-column address lines)................. 11-24 11-19 mcf5407 to sdram interface (8-bit port,13-column address lines)................. 11-25 11-20 mcf5407 to sdram interface (16-bit port, 8-column address lines)................ 11-25 11-21 mcf5407 to sdram interface (16-bit port, 9-column address lines)................ 11-25 11-22 mcf5407 to sdram interface (16-bit port, 10-column address lines).............. 11-25 11-23 mcf5407 to sdram interface (16-bit port, 11-column address lines).............. 11-25 11-24 mcf5407 to sdram interface (16-bit port, 12-column address lines).............. 11-26 xxxii mcf5407 user?s manual tables table number title page number 11-25 mcf5407 to sdram interface (16-bit port, 13-column-address lines) ............. 11-26 11-26 mcf5407 to sdram interface (32-bit port, 8-column address lines)................ 11-26 11-27 mcf5407 to sdram interface (32-bit port, 9-column address lines)................ 11-26 11-28 mcf5407 to sdram interface (32-bit port, 10-column address lines).............. 11-26 11-29 mcf5407 to sdram interface (32-bit port, 11-column address lines).............. 11-27 11-30 mcf5407 to sdram interface (32-bit port, 12-column address lines).............. 11-27 11-31 sdram hardware connections............................................................................... 11-27 11-32 sdram example specifications ............................................................................. 11-34 11-33 sdram hardware connections............................................................................... 11-35 11-34 dcr initialization values......................................................................................... 11-35 11-35 dacr initialization values...................................................................................... 11-36 11-36 dmr0 initialization values...................................................................................... 11-37 11-37 mode register initialization ..................................................................................... 11-38 12-1 dma signals .............................................................................................................. 12 -2 12-2 mcf5407 signal configurations for pp[4:2]/tm[2:0]/d a ck [1:0] .......................... 12-3 12-3 memory map for dma controller module registers................................................ 12-6 12-4 dcrn field descriptions............................................................................................ 12-8 12-5 dsrn field descriptions .......................................................................................... 12-10 13-1 general-purpose timer module memory map .......................................................... 13-3 13-2 tmrn field descriptions ........................................................................................... 13-4 13-3 tern field descriptions............................................................................................. 13-6 13-4 time-out values (in seconds)?trr[ref] = 0xffff(162-mhz processor clock) 13-7 14-1 uart module programming model.......................................................................... 14-4 14-2 umr1n field descriptions ......................................................................................... 14-6 14-3 umr2n field descriptions ......................................................................................... 14-7 14-4 rxlvl field descriptions......................................................................................... 14-8 14-5 modem control register (modctl) field descriptions.......................................... 14-9 14-6 txlvl field descriptions ....................................................................................... 14-10 14-7 usrn field descriptions .......................................................................................... 14-11 14-8 ucsrn field descriptions........................................................................................ 14-12 14-9 rsmp field descriptions ......................................................................................... 14-13 14-10 tspc field descriptions........................................................................................... 14-13 14-11 ucrn field descriptions.......................................................................................... 14-14 14-12 uipcrn field descriptions ...................................................................................... 14-17 14-13 uacrn field descriptions ....................................................................................... 14-18 14-14 uisrn/uimrn field descriptions ........................................................................... 14-19 14-15 uivrn field descriptions ........................................................................................ 14-20 14-16 uipn field descriptions............................................................................................ 14-20 14-17 uop1/uop0 field descriptions ............................................................................... 14-21 14-18 uart module signals ............................................................................................. 14-22 14-19 uart module initialization sequence .................................................................... 14-38 15-1 parallel port pin descriptions ..................................................................................... 15-2 15-2 paddr field description .......................................................................................... 15-2 tables xxxiii tables table number title page number 15-3 relationship between padat register and parallel port pin (pp) ........................... 15-3 16-1 pins 1?52 (left, top-to-bottom) ................................................................................ 16-1 16-2 pins 53?104 (bottom, left-to-right).......................................................................... 16-3 16-3 pins 105?156 (right, bottom-to-top)........................................................................ 16-5 16-4 pins 157?208 (top, right-to-left) ............................................................................. 16-6 16-5 dimensions ............................................................................................................... 16 -11 17-1 mcf5407 signal index............................................................................................... 17-3 17-2 mcf5407 alphabetical signal index ......................................................................... 17-5 17-3 data pin configuration ............................................................................................... 17-8 17-4 bus cycle size encoding............................................................................................ 17-9 17-5 bus cycle transfer type encoding.......................................................................... 17-10 17-6 tm[2:0] encodings for tt = 00 (normal access)................................................... 17-10 17-7 tm2 encoding for dma as master (tt = 01) ......................................................... 17-11 17-8 tm[1:0] encoding for dma as master (tt = 01) ................................................... 17-11 17-9 tm[2:0] encodings for tt = 10 (emulator access) ................................................ 17-11 17-10 tm[2:0] encodings for tt = 11 (interrupt level) ................................................... 17-12 17-11 data pin configuration ............................................................................................. 17-14 17-12 d7 selection of cs0 automatic acknowledge ........................................................ 17-14 17-13 d6 and d5 selection of cs0 port size ..................................................................... 17-14 17-14 d3/be_config, be[3:0] boot configuration ....................................................... 17-15 17-15 d4/addr_config, address pin assignment....................................................... 17-15 18-1 coldfire bus signal summary ................................................................................... 18-1 18-2 bus cycle size encoding............................................................................................ 18-3 18-3 accesses by matches in cscrs and dacrs ............................................................. 18-5 18-4 bus cycle states ......................................................................................................... 18 -6 18-5 allowable line access patterns ............................................................................... 18-12 18-6 mcf5407 arbitration protocol states ...................................................................... 18-20 18-7 coldfire bus arbitration signal summary............................................................... 18-21 18-8 cycles for basic no-wait-state external master access......................................... 18-23 18-9 cycles for external master burst line access to 32-bit port .................................. 18-24 18-10 mcf5407 two-wire bus arbitration protocol transition conditions.................... 18-28 18-11 three-wire bus arbitration protocol transition conditions ................................... 18-32 18-12 data pin configuration ............................................................................................. 18-35 19-1 jtag pin descriptions ............................................................................................... 19-3 19-2 jtag instructions....................................................................................................... 19- 5 19-3 idcode bit assignments.......................................................................................... 19-6 19-4 boundary-scan bit definitions................................................................................... 19-7 20-1 absolute maximum ratings ....................................................................................... 20-1 20-2 operating temperatures.............................................................................................. 20-1 20-3 dc electrical specifications ....................................................................................... 20-2 20-4 divide ratio encodings .............................................................................................. 20-4 20-5 clock timing specification ........................................................................................ 20-5 20-6 input ac timing specification................................................................................... 20-6 xxxiv mcf5407 user?s manual tables table number title page number 20-7 output ac timing specification ................................................................................ 20-6 20-8 reset timing specification....................................................................................... 20-15 20-9 debug ac timing specification .............................................................................. 20-16 20-10 timer module ac timing specification.................................................................. 20-17 20-11 i 2 c input timing specifications between scl and sda......................................... 20-18 20-12 i 2 c output timing specifications between scl and sda ...................................... 20-18 20-13 uart module ac timing specifications ............................................................... 20-19 20-14 general-purpose i/o port ac timing specifications............................................... 20-22 20-15 dma ac timing specifications .............................................................................. 20-23 20-16 ieee 1149.1 (jtag) ac timing specifications ..................................................... 20-24 a-1 differences between mcf5307 and mcf5407........................................................... a-1 a-2 movec cpu space register map ............................................................................. a-4 a-3 tm[2:1] encoding for mcf5307 internal dma as master (tt = 01) ....................... a-4 a-4 tm0 encoding for mcf5307 internal dma as master (tt = 01) ............................. a-5 a-5 divide ratio encodings ............................................................................................... a-7 a-6 d[7:0] multiplexing ..................................................................................................... a-8 a-7 d7/aa, automatic acknowledge of boot cs0........................................................... a-9 a-8 d[6:5]/ps[1:0], port size of boot cs0 ........................................................................ a-9 a-9 d4/addr_config, address pin assignment.......................................................... a-9 a-10 d3/be_config, be[3:0] boot configuration .......................................................... a-9 a-11 definition of drc encoding?write ......................................................................... a-13 a-12 debug c exception vector assignments .................................................................. a-16 a-13 version 4 debug c processor status encodings ....................................................... a-17 b-1 sim registers............................................................................................................... .b-1 b-2 interrupt controller registers .......................................................................................b-1 b-3 chip-select registers....................................................................................................b-2 b-4 dram controller registers .........................................................................................b-3 b-5 general-purpose timer registers .................................................................................b-4 b-6 uart0 control registers.............................................................................................b-4 b-7 uart1 control registers.............................................................................................b-6 b-8 parallel port memory map............................................................................................b-7 b-9 i 2 c interface memory map...........................................................................................b-8 b-10 dma controller registers............................................................................................b-8 about this book xxxv about this book the primary objective of this user?s manual is to de ne the functionality of the mcf5407 processors for use by software and hardware developers. the information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. as with any technical documentation, it is the readers? responsibility to be sure they are using the most recent version of the documentation. to locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/cold re. audience this manual is intended for system software and hardware developers and applications programmers who want to develop products for the mcf5407. it is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the coldfire architecture. organization following is a summary and a brief description of the major sections of this manual: chapter 1, ?overview,? includes general descriptions of the modules and features incorporated in the mcf5407, focussing in particular on new features de ned by the version 4 (v4) programming model, such as the harvard memory architecture implementation, new instructions, and new registers. part i is intended for system designers who need to understand the operation of the mcf5407 coldfire core and its multiply/accumulate (mac) execution unit. it describes the programming and exception models, harvard memory implementation, and debug module. ? chapter 2, ?coldfire core,? provides an overview of the microprocessor core of the mcf5407. the chapter begins with a description of enhancements from the v3 coldfire core, and then fully describes the v4 programming model as it is implemented on the mcf5407. it also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. xxxvi mcf5407 user?s manual organization ? chapter 3, ?hardware multiply/accumulate (mac) unit,? describes the mcf5407 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. the mac is integrated into the operand execution pipeline (oep). ? chapter 4, ?local memory.? this chapter describes the mcf5407 implementation of the coldfire v4 local memory speci cation. it consists of the two following major sections. ? section 4.2, ?sram overview,? describes the mcf5407 on-chip static ram (sram) implementation. it covers general operations, con guration, and initialization. it also provides information and examples showing how to minimize power consumption when using the sram. ? section 4.7, ?cache overview,? describes the mcf5407 cache implementation, including organization, con guration, and coherency. it describes cache operations and how the cache interacts with other memory structures. ? chapter 5, ?debug support,? describes the revision c enhanced hardware debug support in the mcf5407. this revision of the coldfire debug architecture encompasses earlier revisions. part ii, ?system integration module (sim),? describes the system integration module, which provides overall control of the bus and serves as the interface between the coldfire core processor complex and internal peripheral devices. it includes a general description of the sim and individual chapters that describe components of the sim, such as the phase-lock loop (pll) timing source, interrupt controller for peripherals, con guration and operation of chip selects, and the sdram controller. ? chapter 6, ?sim overview,? describes the sim programming model, bus arbitration, and system-protection functions for the mcf5407. ? chapter 7, ?phase-locked loop (pll),? describes con guration and operation of the pll module. it describes in detail the registers and signals that support the pll implementation. ? chapter 8, ?i2c module,? describes the mcf5407 i 2 c module, including i 2 c protocol, clock synchronization, and the registers in the i 2 c programing model. it also provides extensive programming examples. ? chapter 9, ?interrupt controller,? describes operation of the interrupt controller portion of the sim. includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. ? chapter 10, ?chip-select module,? describes the mcf5407 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers. ? chapter 11, ?synchronous/asynchronous dram controller module,? describes con guration and operation of the synchronous/asynchronous dram about this book xxxvii organization controller component of the sim. it begins with a general description and brief glossary, and includes a description of signals involved in dram operations. the remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. part iii, ?peripheral module,? describes the operation and con guration of the mcf5407 dma, timer, uart, and parallel port modules, and describes how they interface with the system integration unit, described in part ii. ? chapter 12, ?dma controller module,? provides an overview of the dma controller module and describes in detail its signals and registers. the latter sections of this chapter describe operations, features, and supported data transfer modes in detail, showing timing diagrams for various operations. ? chapter 13, ?timer module,? describes con guration and operation of the two general-purpose timer modules, timer 0 and timer 1. it includes programming examples. ? chapter 14, ?uart modules,? describes the use of the universal asynchronous/synchronous receiver/transmitters (uarts) implemented on the mcf5407 and includes programming examples. particular attention is given to the uart1 implementation of a synchronous interface that provides a controller for an 8- or 16-bit codec interface and an audio codec ?97 (ac ?97) digital interface. ? chapter 15, ?parallel port (general-purpose i/o),? describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. it includes a code example for setting up the parallel port. part iv, ?hardware interface,? provides a pinout and both electrical and functional descriptions of the mcf5407 signals. it also describes how these signals interact to support the variety of bus operations shown in timing diagrams. ? chapter 16, ?mechanical data,? provides a functional pin listing and package diagram for the mcf5407. ? chapter 17, ?signal descriptions,? provides an alphabetical listing of mcf5407 signals. this chapter describes the mcf5407 signals. in particular, it shows which are inputs or outputs, how they are multiplexed, which signals require pull-up resistors, and the state of each signal at reset. ? chapter 18, ?bus operation,? describes data transfers, error conditions, bus arbitration, and reset operations. it describes transfers initiated by the mcf5407 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. note that chapter 11, ?synchronous/asynchronous dram controller module,? describes dram cycles. ? chapter 19, ?ieee 1149.1 test access port (jtag),? describes con guration and operation of the mcf5407 jtag test implementation. it describes the use of jtag instructions and how to disable jtag functionality. xxxviii mcf5407 user?s manual suggested reading ? chapter 20, ?electrical speci cations,? describes ac and dc electrical speci cations and thermal characteristics for the mcf5407. because additional speeds may have become available since the publication of this book, consult motorola?s coldfire web page, http://www.motorola.com/cold re, to con rm that this is the latest information. this manual includes the following two appendixes: appendix a, ?migrating from the coldfire mcf5307 to the mcf5407,? highlights the differences between the mcf5307b and mcf5407. users of the mcf5307 and mcf5307a should use this document in conjunction with the mcf5307 user's manual mask set addendum . for additional information, see the mcf5407 integrated coldfire microprocessor product brief . appendix b, ?list of memory maps,? lists the entire address-map for mcf5407 memory-mapped registers. this manual also includes a glossary and an index. suggested reading this section lists additional reading that provides background for the information in this manual as well as general information about the coldfire architecture. general information the following documentation provides useful information about the coldfire architecture and computer architecture in general: coldfire documentation the coldfire documentation is available from the sources listed on the back cover of this manual. document order numbers are included in parentheses for ease in ordering. coldfire programmers reference manual, r1.0 (mcf5200prm/ad) user?s manuals?these books provide details about individual coldfire implementations and are intended to be used in conjunction with the coldfire programmers reference manual. these include the following: ? coldfire mcf5102 user?s manual (mcf5102um/ad) ? coldfire mcf5202 user?s manual (mcf5202um/ad) ? coldfire mcf5204 user?s manual (mcf5204um/ad) ? coldfire mcf5206 user?s manual (mcf5206eum/ad) ? coldfire mcf5206e user?s manual (mcf5206eum/ad) ? coldfire mcf5307 user?s manual (mcf5307um/ad) coldfire programmers reference manual, r1.0 (mcf5200prm/ad) about this book xxxix conventions using microprocessors and microcomputers: the motorola family, william c. wray, ross bannatyne, joseph d. green eld additional literature on coldfire implementations is being released as new processors become available. for a current list of coldfire documentation, refer to the world wide web at http://www.motorola.com/coldfire/. conventions this document uses the following notational conventions: mnemonics in text, instruction mnemonics are shown in uppercase. mnemonics in code and tables, instruction mnemonics are shown in lowercase. italics italics indicate variable command parameters. book titles in text are set in italics. 0x0 pre x to denote hexadecimal number 0b0 pre x to denote binary number reg[field] abbreviations for registers are shown in uppercase. speci c bits, elds, or ranges appear in brackets. for example, rambar[ba] identi es the base address eld in the ram base address register. nibble a 4-bit data unit byte an 8-bit data unit word a 16-bit data unit longword a 32-bit data unit x in some contexts, such as signal encodings, x indicates a don?t care. n used to express an unde ned numerical value ? not logical operator & and logical operator | or logical operator acronyms and abbreviations table i lists acronyms and abbreviations used in this document. table i. acronyms and abbreviated terms term meaning adc analog-to-digital conversion alu arithmetic logic unit avec autovector xl mcf5407 user?s manual acronyms and abbreviations bdm background debug mode bist built-in self test bsdl boundary-scan description language codec code/decode dac digital-to-analog conversion dma direct memory access dsp digital signal processing ea effective address edo extended data output (dram) fifo first-in, ?st-out gpio general-purpose i/o i 2 c inter-integrated circuit ieee institute for electrical and electronics engineers ifp instruction fetch pipeline ipl interrupt priority level jedec joint electron device engineering council jtag joint test action group lifo last-in, ?st-out lru least recently used lsb least-signi?ant byte lsb least-signi?ant bit mac multiple accumulate unit mbar memory base address register msb most-signi?ant byte msb most-signi?ant bit mux multiplex nop no operation oep operand execution pipeline pc program counter pclk processor clock pll phase-locked loop plru pseudo least recently used table i. acronyms and abbreviated terms (continued) term meaning about this book xli terminology and notational conventions terminology and notational conventions table ii shows notational conventions used throughout this document. por power-on reset pqfp plastic quad ?t pack risc reduced instruction set computing rx receive sim system integration module sof start of frame tap test access port ttl transistor-to-transistor logic tx transmit uart universal asynchronous/synchronous receiver transmitter table ii notational conventions instruction operand syntax opcode wildcard cc logical condition (example: ne for not equal) register speci cations an any address register n (example: a3 is address register 3) ay,ax source and destination address registers, respectively dn any data register n (example: d5 is data register 5) dy,dx source and destination data registers, respectively rc any control register (example vbr is the vector base register) rm mac registers (acc, mac, mask) rn any address or data register rw destination register w (used for mac instructions only) ry,rx any source and destination registers, respectively xi index register i (can be an address or data register: ai, di) table i. acronyms and abbreviated terms (continued) term meaning xlii mcf5407 user?s manual terminology and notational conventions register names acc mac accumulator register ccr condition code register (lower byte of sr) macsr mac status register mask mac mask register pc program counter sr status register port name pstddata processor status/debug data port miscellaneous operands # immediate data following the 16-bit operation word of the instruction |